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Thursday, June 23 • 1:30pm - 1:45pm
Getting Started with RISC-V Custom Instructions - Larry Lapides, Imperas Software Ltd

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One of the attractive features of RISC-V is the ability to add, while maintaining ecosystem software support, new optimized instructions and extensions to a processor implementation. At first it appears as simple task to look at opportunities in the application code that could be accelerated with some dedicated new hardware. However, since hardware typically has a much longer life cycle than software, future updates and roadmap needs must be anticipated. Thus, the art of ISA design is using fine grain analysis to accelerate just the key steps while leaving sufficient flexibility to support new software updates and advances. Also, in multi-core arrays the use of custom extension can offer a lightweight communication channel between processors. This extends the scope beyond the processor itself into system design and analysis. This talk will illustrate the key profiling and analysis steps for custom extensions and optimization.

Speakers
avatar for Larry Lapides

Larry Lapides

VP Sales & Marketing, Imperas Software
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before... Read More →



Thursday June 23, 2022 1:30pm - 1:45pm CEST
Hall 1, Booth #1-550
  Demo
  • Slides Attached Yes