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10:00am • Introduction to RISC-V Processor Verification - Larry Lapides, Imperas Software Ltd
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10:30am • Introducing SiFive Vector Processor Portfolio - Andrew Frame, SiFive
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11:00am • The Next Step in Low Energy Edge DSP and AI - Martin Croome, GreenWaves Technologies
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11:30am • Customizing RISC-V Cores to Accelerate Neural Networks - Jon Taylor, Codasip
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12:00pm • Ubuntu Core: A Secured Embedded Linux Distribution for RISC-V - Ondrej Kubik, Canonical
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1:00pm • RISC-V and Functional Safety - Florian Wohlrab, Andes Technology
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1:30pm • OpenHW CORE-V MCU DevKit for Cloud Connected IoT - Rick O'Connor, OpenHW Group
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2:00pm • Open Acceleration for RISC-V – Portability, Performance and Partners Achieved with SYCL Instead of CUDA - Charles Macfarlane, Codeplay
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2:30pm • NOEL-V, a Configurable 32-Bit and 64-bit RISC-V IP - Christian Sayer, Cobham Gaisler
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3:00pm • Remote Development with SCRx-based SDK - Hugo Décharnes, Syntacore
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3:30pm • Thermal (IR) Imaging Camera including ISP on Polarfire RISC-V FPGA SoC - S Thomas, Digital Core Technologies
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10:30am • Thermal (IR) Imaging Camera including ISP on Polarfire RISC-V FPGA SoC - S Thomas, Digital Core Technologies
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11:00am • NOEL-V, a Configurable 32-Bit and 64-bit RISC-V IP - Christian Sayer, Cobham Gaisler
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11:30am • Running Quake on RISC-V with Virtual Platforms - Kevin McDermott, Imperas Software Ltd
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12:00pm • Remote Development with SCRx-based SDK - Hugo Décharnes, Syntacore
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1:00pm • Design for Differentiation: Architecture Licenses in RISC-V - Filip Benna, Codasip
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1:30pm • Linux Made Easy on RISC-V with Ubuntu - Gordan Markus, Canonical
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2:00pm • RISC-V and Functional Safety - Florian Wohlrab, Andes Technology
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2:30pm • OpenHW CORE-V MCU DevKit for Cloud Connected IoT - Rick O'Connor, OpenHW Group
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3:00pm • The Next Generation SiFive Intelligence X280 - Drew Barbier, SiFive
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3:30pm • Open Acceleration for RISC-V – Portability, Performance and Partners Achieved with SYCL Instead of CUDA - Charles Macfarlane, Codeplay
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4:00pm • The Next Step in Low Energy Edge DSP and AI - Martin Croome, GreenWaves Technologies
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10:00am • OpenHW CORE-V MCU DevKit for Cloud Connected IoT - Rick O'Connor, OpenHW Group
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10:30am • I Fought the Law and the Law Lost: Moore’s Law, Dennard Scaling & RISC-V - Rupert Baines, Codasip
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11:00am • Developing Containerized RISC-V Applications with Ubuntu - Heinrich Schuchardt, Canonical
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11:30am • NOEL-V, a Configurable 32-Bit and 64-bit RISC-V IP - Christian Sayer, Cobham Gaisler
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12:00pm • RISC-V and Functional Safety - Florian Wohlrab, Andes Technology
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1:00pm • The Next Step in Low Energy Edge DSP and AI - Martin Croome, GreenWaves Technologies
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1:30pm • Getting Started with RISC-V Custom Instructions - Larry Lapides, Imperas Software Ltd
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2:00pm • Securing SiFive Vector Processors with an Open, Scalable Security Architecture - Dany Nativel, SiFive
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2:30pm • Thermal (IR) Imaging Camera including ISP on Polarfire RISC-V FPGA SoC - S Thomas, Digital Core Technologies
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3:00pm • RISC-V: Data Center Transformation - Travis Lanier, Ventana
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3:30pm • Remote Development with SCRx-based SDK - Hugo Décharnes, Syntacore
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4:00pm • Open Acceleration for RISC-V – Portability, Performance and Partners Achieved with SYCL Instead of CUDA - Charles Macfarlane, Codeplay
